A semiconductor integrated circuit (IC) is required to be resistant to surge voltage and surge current caused by electrostatic discharge (ESD) and loaded on the input/output pad of the IC. In order to meet this requirement, an ESD protection circuit is generally connected to the input/output pad of IC. As such an ESD protection circuit, a MOS-type protection device that performs a parasitic bipolar transistor operation is used.
FIG. 9 is a circuit diagram of a conventional ESD protection circuit using a MOS-type protection device. In FIG. 9, an n-type MOSFET 101 has its drain connected to a pad 102 while its gate, backgate, and source are grounded in common. When a positive ESD surge is applied to the pad 102, the n-type MOSFET 101 performs a parasitic bipolar transistor operation because of the breakdown of the p-n junction between the drain and the backgate, and functions so as to release the surge current from the pad 102 to the ground. Further, when a negative ESD surge is applied to the pad 102, the n-type MOSFET 101 functions so as to release the surge current from the ground to the pad 102 since the p-n junction between the drain and the backgate is forward-biased.
When a positive signal is supplied to the pad 102, the signal is not attenuated by the n-type MOSFET 101 since the drain-backgate junction of the n-type MOSFET 101 is reverse-biased. However, when a signal having a larger value than the forward voltage drop of the p-n junction in the negative direction is supplied to the pad 102, the drain-backgate junction of the n-type MOSFET 101 is forward-biased, the signal flows through the n-type MOSFET 101, and the attenuation of the signal occurs. Note that, if the MOSFET 101 is p-type, the attenuation of signal will occur when a positive signal is supplied to the pad 102.
In Patent Document 1, an ESD protection circuit that does not attenuate signals even when a signal larger than the power supply voltage is supplied to the input terminal is disclosed. As shown in FIG. 10A, this ESD protection circuit comprises an input terminal 111, a power supply terminal (Vdd) 112, an N-well (backgate), and a P-channel transistor 113 having its drain and source (or source and drain) connected to the input terminal and the power supply terminal respectively in the N-well. A gate of the P-channel transistor 113 is connected to the N-well and the gate and the N-well are in a floating state.
Further, another configuration in which a second P-channel transistor 114 having its drain and source or source and drain connected to the input terminal 111 and the gate of the P-channel transistor 113 respectively and a gate of the second P-channel transistor 114 is connected to the power supply terminal Vdd as shown in FIG. 10B is disclosed in Patent Document 1. According to Patent Document 1, the second P-channel transistor 114 is said to help increasing the gate potential of the first P-channel transistor 113, thereby further improving the protection capability.
Further, as shown in FIG. 11, an NMOS transistor 120 having its source grounded, its drain connected to a pad 116, and its gate and backgate (P-well) grounded via an NMOS transistor 128 is disclosed as an ESD protection circuit in Patent Document 2. The NMOS transistor 128 is controlled by a gate 125 so that it turns on when the circuit operates and turns off when no current is supplied to the chip. Further, a backgate of the NMOS transistor 128 is grounded according to Patent Document 2.
[Patent Document 1]    Japanese Patent Kokai Publication No. JP-A-7-147381
[Patent Document 2]    U.S. Pat. No. 6,399,990B1 (Description)